Data Sheet
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Continuity of Specifications
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Publication Number 23579 Revision CAmendment +3 Issue Date September 19, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV320D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■Secured Silicon (SecSiTM Sector)
— Kbyte Sector Size; Replacement/substitute
devices (such as Mirrorbit™) have 256 bytes.
—Factory locked and identifiable: 16 bytes (8 words)
available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data—Customer lockable: Can be programmed once and
then permanently locked after being shipped from AMD■Zero Power Operation
—Sophisticated power management circuits reduce
power consumed during inactive periods to nearly zero.
■Package options
—48-pin TSOP—48-ball FBGA■Sector Architecture
—Eight 8 Kbyte sectors
—Sixty-three Kbyte sectors■Top or bottom boot block
■Manufactured on 0.23 µm process technology■Compatible with JEDEC standards
—Pinout and software compatible with
single-power-supply flash standard
■Minimum 1 million erase cycles guaranteed per
sector
■20 Year data retention at 125°C
—Reliable operation for the life of the system
SOFTWARE FEATURES
■Supports Common Flash Memory Interface (CFI)■Erase Suspend/Erase Resume
—Suspends erase operations to allow programming in
non-suspended sectors
■Data# Polling and Toggle Bits
—Provides a software method of detecting the status of
program or erase cycles
■Unlock Bypass Program command
—Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■Any combination of sectors can be erased ■Ready/Busy# output (RY/BY#)
—Hardware method for detecting program or erase
cycle completion
■Hardware reset pin (RESET#)
—Hardware method of resetting the internal state
machine to the read mode
■WP#/ACC input pin
—Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
—Acceleration (ACC) function provides accelerated
program times
■Sector protection
—Hardware method of locking a sector, either
in-system or using programming equipment, to prevent any program or erase operation within that sector
—Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
■High performance
—Access time as fast 90 ns
—Program time: 7µs/word typical utilizing Accelerate
function
■Ultra low power consumption (typical values)
—2 mA active read current at 1 MHz—10 mA active read current at 5 MHz
—200 nA in standby or automatic sleep mode
Publication# 23579Rev: CAmendment/+3Issue Date: September 19, 2003
GENERAL DESCRIPTION
The Am29LV320D is a 32 megabit, 3.0 volt-only flashmemory device, organized as 2,097,152 words of 16bits each or 4,194,304 bytes of 8 bits each. Wordmode data appears on DQ0–DQ15; byte mode dataappears on DQ0–DQ7. The device is designed to beprogrammed in-system with the standard 3.0 volt VCCsupply, andcan also be programmed in standardEPROM programmers.
The device is available with an access time of 90 or120 ns. The devices are offered in 48-pin TSOP and48-ball FBGA packages. Standard control pins—chipenable (CE#), write enable (WE#), and output enable(OE#)—control normal read and write operations, andavoid bus contention issues.
The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for theprogram and erase operations.
both. Customer Lockable parts may utilize the SecSiSector as bonus space, reading and writing like anyother flash sector, or may permanently lock their owncode there.
The device offers complete compatibility with theJEDEC single-power-supply Flash command setstandard. Commands are written to the commandregister using standard microprocessor write timings.Reading data out of the device is similar to readingfrom other Flash or EPROM devices.
The host system can detect whether a program orerase operation is complete by using the device sta-tus bits: RY/BY# pin, DQ7 (Data# Polling) andDQ6/DQ2 (toggle bits). After a program or erase cyclehas been completed, the device automatically returnsto the read mode.
The sector erase architecture allows memory sec-tors to be erased and reprogrammed without affectingthe data contents of other sectors. The device is fullyerased when shipped from the factory.
Hardware data protection measures include a lowVCC detector that automatically inhibits write opera-tions during power transitions. The hardware sectorprotection feature disables both program and eraseoperations in any combination of the sectors of mem-ory. This can be achieved in-system or via program-ming equipment.
The device offers two power-saving features. Whenaddresses have been stable for a specified amount oftime, the device enters the automatic sleep mode.The system can also place the device into thestandby mode. Power consumption is greatly re-duced in both modes.
Am29LV320D Features
The SecSiTM Sector (Secured Silicon) is an extrasector capable of being permanently locked by AMDor customers. The SecSi Indicator Bit (DQ7) is per-manently set to a 1 if the part is factory locked, andset to a 0 if customer lockable. This way, customerlockable parts can never be used to replace a factorylocked part. Note that the Am29LV320D has a SecSiSector size of Kbytes. AMD devices designatedas replacements or substitutes, such as theAm29LV320M, will have 256 bytes. This should beconsidered during system design.
Factory locked parts provide several options. TheSecSi Sector may store a secure, random 16 byteESN (Electronic Serial Number), customer code (pro-grammed through AMD’s ExpressFlash service), or
2Am29LV320DSeptember 19, 2003
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5Special Package Handling Instructions ....................................6Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9Word/Byte Configuration ..........................................................9Requirements for Reading Array Data .....................................9Writing Commands/Command Sequences ............................10Accelerated Program Operation ..........................................10Autoselect Functions ...........................................................10Standby Mode ........................................................................10Automatic Sleep Mode ...........................................................10RESET#: Hardware Reset Pin ...............................................11Output Disable Mode ..............................................................11Autoselect Mode .....................................................................16Sector/Sector Block Protection and Unprotection ..................17Write Protect (WP#) ................................................................18Temporary Sector Unprotect ..................................................18
Figure 1. Temporary Sector Unprotect Operation........................... 18Figure 2. In-System Sector Protect/UnprotectAlgorithms.............. 19
DQ2: Toggle Bit II ...................................................................32Reading Toggle Bits DQ6/DQ2 ...............................................32DQ5: Exceeded Timing Limits ................................................32DQ3: Sector Erase Timer .......................................................32Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative OvershootWaveform...................... 34Figure 9. Maximum Positive OvershootWaveform........................ 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. ICC1 Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 36Figure 11. Typical ICC1 vs. Frequency............................................ 36Figure 12. Test Setup.................................................................... 37Figure 13. Input Waveforms and Measurement Levels................. 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. Read Operation Timings............................................... 38Figure 15. Reset Timings............................................................... 39
Word/Byte Configuration (BYTE#) .............................................40
Figure 16. BYTE# Timings for Read Operations............................ 40Figure 17. BYTE# Timings for Write Operations............................ 40
Erase and Program Operations .................................................41
Figure 18. Program Operation Timings.......................................... 42Figure 19. Chip/Sector Erase Operation Timings.......................... 43Figure 20. Data# Polling Timings (DuringEmbeddedAlgorithms). 44Figure 21. Toggle Bit Timings (DuringEmbeddedAlgorithms)...... 45Figure 22. DQ2 vs. DQ6................................................................. 45
SecSiTM Sector (Secured Silicon) Flash Memory Region .......20Factory Locked: SecSi Sector Programmed
andProtectedattheFactory ...............................................20Customer Lockable: SecSi Sector NOT Programmed
orProtectedattheFactory ..................................................20
Figure 3. SecSi Sector Protect Verify.............................................. 21
Temporary Sector Unprotect .....................................................46
Figure 23. Temporary Sector Unprotect TimingDiagram.............. 46Figure 24. Accelerated Program Timing Diagram.......................... 46Figure 25. Sector/Sector Block Protect and
UnprotectTimingDiagram............................................................. 47
Hardware Data Protection ......................................................21Low VCC Write Inhibit .........................................................21Write Pulse “Glitch” Protection ............................................21Logical Inhibit ......................................................................21Power-Up Write Inhibit .........................................................21Common Flash Memory Interface (CFI) . . . . . . .21Command Definitions . . . . . . . . . . . . . . . . . . . . . .25Reading Array Data ................................................................25Reset Command .....................................................................25Autoselect Command Sequence ............................................25Enter SecSiTM Sector/Exit SecSi Sector
CommandSequence ..............................................................25Byte/Word Program Command Sequence .............................26Unlock Bypass Command Sequence ..................................26
Figure 4. Program Operation.......................................................... 27
Alternate CE# Controlled Erase and ProgramOperations ........48
Figure 26. Alternate CE# Controlled Write
(Erase/Program)OperationTimings.............................................. 49
Chip Erase Command Sequence ...........................................27Sector Erase Command Sequence ........................................27Erase Suspend/Erase Resume Commands ...........................28
Figure 5. Erase Operation............................................................... 28
Command Definitions .............................................................29Write Operation Status . . . . . . . . . . . . . . . . . . . . .30DQ7: Data# Polling .................................................................30
Figure 6. Data# Polling Algorithm................................................... 30
RY/BY#: Ready/Busy# ...........................................................31DQ6: Toggle Bit I ....................................................................31
Figure 7. Toggle Bit Algorithm......................................................... 31
Erase And Programming Performance . . . . . . . 50Latchup Characteristics . . . . . . . . . . . . . . . . . . . 50TSOP and BGA Package Capacitance . . . . . . . . 50Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)
6x12mm package ...................................................................51TS 048—48-Pin Standard TSOP ...............................................52Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53Revision A (November 1, 2000) ..............................................53Revision A+1 (January 23, 2001) ...........................................53Revision A+2 (February 1, 2001) ............................................53Revision A+3 (July 2, 2001) ....................................................53Revision B (July 12, 2002) ......................................................53Revision B+1 (July 30, 2002) ..................................................53Revision C (October 25, 2002) ...............................................53Revision C+1 (February 16, 2003) .........................................53Revision C+2 (April 4, 2003) ...................................................54Revision C+3 (September 19, 2003) ......................................54
September 19, 2003Am29LV320D3
PRODUCT SELECTOR GUIDE
Family Part NumberSpeed OptionMax Access Time (ns)CE# Access (ns)OE# Access (ns)
Standard Voltage Range: VCC = 2.7–3.6 V
Am29LV320D90909040
12012012050
BLOCK DIAGRAM
RY/BY#
VCCVSS
RESET#
Sector SwitchesErase VoltageGenerator
Input/OutputBuffersDQ0–DQ15 (A-1)
WE#BYTE#
StateControlCommandRegister
PGM VoltageGenerator
Chip EnableOutput Enable
Logic
STB
DataLatch
CE#OE#
STB
VCC Detector
Timer
Address LatchY-DecoderY-Gating
X-Decoder
Cell Matrix
A0–A20
4Am29LV320DSeptember 19, 2003
CONNECTION DIAGRAMS
A15A14A13A12A11A10A9A8A19A20WE#RESET#NCWP#/ACCRY/BY#A18A17A7A6A5A4A3A2A1123456710111213141516171819202122232448-Pin Standard TSOP4847454443424140393837363534333231302928272625A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0September 19, 2003Am29LV320D5
CONNECTION DIAGRAMS
48-Ball FBGA
Top View, Balls Facing Down
A6A13A5A9A4WE#A3B6A12B5A8B4RESET#B3C6A14C5A10C4NCC3A18C2A6C1A2D6A15D5A11D4A19D3A20D2A5D1A1E6A16E5DQ7E4DQ5E3DQ2E2DQ0E1A0F6G6H6VSSH5DQ6H4DQ4H3DQ3H2DQ1H1VSSBYTE#DQ15/A-1F5DQ14F4DQ12F3DQ10F2DQ8F1CE#G5DQ13G4VCCG3DQ11G2DQ9G1OE#RY/BY#WP#/ACCA2A7A1A3B2A17B1A4Special Package Handling Instructions
Special handling is required for Flash Memory prod-ucts in molded (TSOP, BGA) packages.
The package and/or data integrity may be compro-mised if the package body is exposed to temperaturesabove 150°C for prolonged periods of time.
6Am29LV320DSeptember 19, 2003
PIN DESCRIPTION
A0–A20
=21 Addresses
DQ0–DQ14=15 Data Inputs/OutputsDQ15/A-1
=DQ15 (Data Input/Output, word
mode), A-1 (LSB Address Input, byte mode)=Chip Enable=Output Enable=Write Enable
=Hardware Write Protect/Acceleration Pin=Hardware Reset Pin, Active Low=Selects 8-bit or 16-bit mode=Ready/Busy Output
=3.0 volt-only single power supply
(see Product Selector Guide for speedoptions and voltage supply toler-ances)=Device Ground
=Pin Not Connected Internally
LOGIC SYMBOL
21
A0–A20
DQ0–DQ15
(A-1)
CE# OE#WE#WP#/ACCRESET#BYTE#
RY/BY#
16 or 8
CE#OE#WE#WP#/ACCRESET#BYTE#RY/BY#VCC
VSSNC
September 19, 2003Am29LV320D7
ORDERING INFORMATIONStandard Products
AMD standard products are available in several packages and operating ranges. The order number (ValidCombination) is formed by a combination of the following:
Am29LV320D
T
90
E
C
TEMPERATURE RANGEI = Industrial (–40°C to +85°C)C =Commercial (0°C to +70°C)
PACKAGE TYPEE=48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
WM=48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 12 mm package (FBD048)SPEED OPTION
See Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET=Top boot sectorB=Bottom boot sector
DEVICE NUMBER/DESCRIPTION
Am29LV320D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Boot Sector Flash Memory3.0 Volt-only Read, Program and Erase
Valid Combinations for TSOP
Packages
AM29LV320DT90R,AM29LV320DB90RAm29LV320DT90,
EC, EI
Am29LV320DB90AM29LV320DT120,AM29LV320DB120
Speed(Ns)9090120
VCCRange3.0– 3.6V2.7– 3.6V2.7– 3.6V
Valid Combinations for FBGA PackagesOrder Number
AM29LV320DT90,AM29LV320DB90AM29LV320DT120,AM29LV320DB120
Package Marking
L320DT90V,
WMC,L320DB90VWMIL320DT12V,
L320DB12V
C, I
Valid Combinations
Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.
8Am29LV320DSeptember 19, 2003
DEVICE BUS OPERATIONS
This section describes the requirements and use ofthe device bus operations, which are initiated throughthe internal command register. The command registeritself does not occupy any addressable memory loca-tion. The register is a latch used to store the com-mands, along with the address and data informationneeded to execute the command. The contents of the
Table 1.
register serve as inputs to the internal state machine.The state machine outputs dictate the function of thedevice. Table 1 lists the device bus operations, the in-puts and control levels they require, and the resultingoutput. The following subsections describe each ofthese operations in further detail.
Am29LV320D Device Bus Operations
DQ8–DQ15
OperationReadWrite
Accelerated ProgramStandbyOutput DisableReset
Sector Protect (Note 2)Sector Unprotect (Note 2)
Temporary Sector Unprotect
CE#LLLVCC ± 0.3 VLXLLX
OE#LHHXHXHHX
WE#HLLXHXLLX
RESET#
HHHVCC ± 0.3 VHLVIDVIDVID
WP#/ACC
L/H(Note 3)VHHHL/HL/HL/H(Note 3)(Note 3)
Addresses(Note 2)
AINAINAINXXX
DQ0–DQ7DOUT
BYTE#= VIHDOUT
BYTE# = VILDQ8–DQ14= High-Z, DQ15 = A-1High-ZHigh-ZHigh-ZXXHigh-Z
(Note 4)(Note 4)(Note 4)(Note 4)High-ZHigh-ZHigh-Z
High-ZHigh-ZHigh-ZXX
SA, A6 = L,
(Note 4)
A1 = H, A0 = L
SA, A6 = H,
(Note 4)
A1 = H, A0 = L
AIN
(Note 4)(Note 4)
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:
1.Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3.If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
4.DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/Opins operate in the byte or word configuration. If theBYTE# pin is set at logic ‘1’, the device is in word con-figuration, DQ0–DQ15 are active and controlled byCE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byteconfiguration, and only data I/O pins DQ0–DQ7 areactive and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin isused as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system mustdrive the CE# and OE# pins to VIL. CE# is the powercontrol and selects the device. OE# is the output con-trol and gates array data to the output pins. WE#should remain at VIH. The BYTE# pin determineswhether the device outputs array data in words orbytes.
September 19, 2003Am29LV320D9
The internal state machine is set for reading array dataupon device power-up, or after a hardware reset. Thisensures that no spurious alteration of the memorycontent occurs during the power transition. No com-mand is necessary in this mode to obtain array data.Standard microprocessor read cycles that assert validaddresses on the device address inputs produce validdata on the device data outputs. The device remainsenabled for read access until the command registercontents are altered.
See “Requirements for Reading Array Data” for moreinformation. Refer to the AC Read-Only Operationstable for timing specifications and to Figure 14 for thetiming diagram. ICC1 in the DC Characteristics tablerepresents the active current specification for readingarray data.
would use a two-cycle program command sequenceas required by the Unlock Bypass mode. RemovingVHH from the WP#/ACC pin returns the device to nor-mal operation. Note that the WP#/ACC pin must notbe at VHH for operations other than accelerated pro-gramming, or device damage may result. In addition,the WP#/ACC pin must not be left floating or uncon-nected; inconsistent behavior of the device may result.Autoselect Functions
If the system writes the autoselect command se-quence, the device enters the autoselect mode. Thesystem can then read autoselect codes from the inter-nal register (which is separate from the memory array)on DQ7–DQ0. Standard read cycle timings apply inthis mode. Refer to the Autoselect Mode and Autose-lect Command Sequence sections for more informa-tion.
ICC6 and ICC7 in the DC Characteristics table representthe current specifications for read-while-program andread-while-erase, respectively.
Writing Commands/Command Sequences
To write a command or command sequence (which in-cludes programming data to the device and erasingsectors of memory), the system must drive WE# andCE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determineswhether the device accepts program data in bytes orwords. Refer to “Word/Byte Configuration” for more in-formation.
The device features an Unlock Bypass mode to facil-itate faster programming. Once the device enters theUnlock Bypass mode, only two write cycles are re-quired to program a word or byte, instead of four. The“Word/Byte Configuration” section has details on pro-gramming data to the device using both standard andUnlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2–5 indicate the ad-dress space that each sector occupies. A “sectoraddress” is the address bits required to uniquely selecta sector.
ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The ACCharacteristics section contains timing specificationtables and timing diagrams for write operations.Accelerated Program Operation
The device offers accelerated program operationsthrough the ACC function. This is one of two functionsprovided by the WP#/ACC pin. This function is prima-rily intended to allow faster manufacturing throughputat the factory.
If the system asserts VHH on this pin, the device auto-matically enters the aforementioned Unlock Bypassmode, temporarily unprotects any protected sectors,and uses the higher voltage on the pin to reduce thetime required for program operations. The system
Standby Mode
When the system is not reading or writing to the de-vice, it can place the device in the standby mode. Inthis mode, current consumption is greatly reduced,and the outputs are placed in the high impedancestate, independent of the OE# input.
The device enters the CMOS standby mode when theCE# and RESET# pins are both held at VCC ± 0.3 V.(Note that this is a more restricted voltage range thanVIH.) If CE# and RESET# are held at VIH, but not withinVCC ± 0.3 V, the device will be in the standby mode,but the standby current will be greater. The device re-quires standard access time (tCE) for read accesswhen the device is in either of these standby modes,before it is ready to read data.
If the device is deselected during erasure or program-ming, the device draws active current until theoperation is completed.
ICC3 in the DC Characteristics table represents thestandby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-ergy consumption. The device automatically enablesthis mode when addresses remain stable for tACC +30ns. The automatic sleep mode is independent ofthe CE#, WE#, and OE# control signals. Standard ad-dress access timings provide new data when ad-dresses are changed. While in sleep mode, outputdata is latched and always available to the system.ICC4 in the DC Characteristics table represents theautomatic sleep mode current specification.
10Am29LV320DSeptember 19, 2003
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-setting the device to reading array data. When the RE-SET# pin is driven low for at least a period of tRP, thedevice immediately terminates any operation inprogress, tristates all output pins, and ignores allread/write commands for the duration of the RESET#pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device isready to accept another command sequence, to en-sure data integrity.
Current is reduced for the duration of the RESET#pulse. When RESET# is held at VSS±0.3 V, the devicedraws CMOS standby current (ICC4). If RESET# is heldat VIL but not within VSS±0.3 V, the standby current willbe greater.
The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-ware from the Flash memory.
If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until theinternal reset operation is complete, which requires atime of tREADY (during Embedded Algorithms). Thesystem can thus monitor RY/BY# to determinewhether the reset operation is complete. If RESET# isasserted when a program or erase operation is not ex-ecuting (RY/BY# pin is “1”), the reset operation is com-pleted within a time of tREADY (not during EmbeddedAlgorithms). The system can read data tRH after theRESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device isdisabled. The output pins are placed in the highimpedance state.
September 19, 2003Am29LV320D11
Table 2.
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30SA31SA32SA33SA34SA35SA36SA37SA38SA39SA40SA41SA42SA43SA44SA45SA46SA47SA48SA49SA50SA51SA52SA53SA54
Sector Address
A20–A12000000xxx000001xxx000010xxx000011xxx000100xxx000101xxx000110xxx000111xxx001000xxx001001xxx001010xxx001011xxx001100xxx001101xxx001110xxx001111xxx010000xxx010001xxx010010xxx010011xxx010100xxx010101xxx010110xxx010111xxx011000xxx011001xxx011010xxx011011xxx011100xxx011101xxx011110xxx011111xxx100000xxx100001xxx100010xxx100011xxx100100xxx100101xxx100110xxx100111xxx101000xxx101001xxx101010xxx101011xxx101100xxx101101xxx101110xxx101111xxx110000xxx110001xxx110010xxx110011xxx110100xxx110101xxx110110xxx
Top Boot Sector Addresses(Am29LV320DT)
(x8)
Address Range000000h–00FFFFh010000h–01FFFFh020000h–02FFFFh030000h–03FFFFh040000h–04FFFFh050000h–05FFFFh060000h–06FFFFh070000h–07FFFFh080000h–08FFFFh090000h–09FFFFh0A0000h–0AFFFFh0B0000h–0BFFFFh0C0000h–0CFFFFh0D0000h–0DFFFFh0E0000h–0EFFFFh0F0000h–0FFFFFh100000h–10FFFFh110000h–11FFFFh120000h–12FFFFh130000h–13FFFFh140000h–14FFFFh150000h–15FFFFh160000h–16FFFFh170000h–17FFFFh180000h–18FFFFh190000h–19FFFFh1A0000h–1AFFFFh1B0000h–1BFFFFh1C0000h–1CFFFFh1D0000h–1DFFFFh1E0000h–1EFFFFh1F0000h–1FFFFFh200000h–20FFFFh210000h–21FFFFh220000h–22FFFFh230000h–23FFFFh240000h–24FFFFh250000h–25FFFFh260000h–26FFFFh270000h–27FFFFh280000h–28FFFFh290000h–29FFFFh2A0000h–2AFFFFh2B0000h–2BFFFFh2C0000h–2CFFFFh2D0000h–2DFFFFh2E0000h–2EFFFFh2F0000h–2FFFFFh300000h–30FFFFh310000h–31FFFFh320000h–32FFFFh330000h–33FFFFh340000h–34FFFFh350000h–35FFFFh360000h–36FFFFh
(x16)
Address Range000000h–07FFFh008000h–0FFFFh010000h–17FFFh018000h–01FFFFh020000h–027FFFh028000h–02FFFFh030000h–037FFFh038000h–03FFFFh040000h–047FFFh048000h–04FFFFh050000h–057FFFh058000h–05FFFFh060000h–067FFFh068000h–06FFFFh070000h–077FFFh078000h–07FFFFh080000h–087FFFh088000h–08FFFFh090000h–097FFFh098000h–09FFFFh0A0000h–0A7FFFh0A8000h–0AFFFFh0B0000h–0B7FFFh0B8000h–0BFFFFh0C0000h–0C7FFFh0C8000h–0CFFFFh0D0000h–0D7FFFh0D8000h–0DFFFFh0E0000h–0E7FFFh0E8000h–0EFFFFh0F0000h–0F7FFFh0F8000h–0FFFFFh100000h–107FFFh108000h–10FFFFh110000h–117FFFh118000h–11FFFFh120000h–127FFFh128000h–12FFFFh130000h–137FFFh138000h–13FFFFh140000h–147FFFh148000h–14FFFFh150000h–157FFFh158000h–15FFFFh160000h–167FFFh168000h–16FFFFh170000h–177FFFh178000h–17FFFFh180000h–187FFFh188000h–18FFFFh190000h–197FFFh198000h–19FFFFh1A0000h–1A7FFFh1A8000h–1AFFFFh1B0000h–1B7FFFh
Sector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32
12Am29LV320DSeptember 19, 2003
Table 2.
SectorSA55SA56SA57SA58SA59SA60SA61SA62SA63SASA65SA66SA67SA68SA69SA70
Sector Address
A20–A12110111xxx111000xxx111001xxx111010xxx111011xxx111100xxx111101xxx111110xxx111111000111111001111111010111111011111111100111111101111111110111111111
Top Boot Sector Addresses(Am29LV320DT) (Continued)
Sector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/328/48/48/48/48/48/48/48/4
(x8)
Address Range370000h–37FFFFh380000h–38FFFFh390000h–39FFFFh3A0000h–3AFFFFh3B0000h–3BFFFFh3C0000h–3CFFFFh3D0000h–3DFFFFh3E0000h–3EFFFFh3F0000h–3F1FFFh3F2000h–3F3FFFh3F4000h–3F5FFFh3F6000h–3F7FFFh3F8000h–3F9FFFh3FA000h–3FBFFFh3FC000h–3FDFFFh3FE000h–3FFFFFh
(x16)
Address Range1B8000h–1BFFFFh1C0000h–1C7FFFh1C8000h–1CFFFFh1D0000h–1D7FFFh1D8000h–1DFFFFh1E0000h–1E7FFFh1E8000h–1EFFFFh1F0000h–1F7FFFh1F8000h–1F8FFFh1F9000h–1F9FFFh1FA000h–1FAFFFh1FB000h–1FBFFFh1FC000h–1FCFFFh1FD000h–1FDFFFh1FE000h–1FEFFFh1FF000h–1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 3.
Sector Address
A20–A12111111xxx
Top Boot SecSiTM Sector Addresses
(x8)
Address Range3F0000h–3FFFFFh
(x16)
Address Range1F8000h–1FFFFFh
Sector Size(Kbytes/Kwords)
/32
September 19, 2003Am29LV320D13
Table 4.
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30SA31SA32SA33SA34SA35SA36SA37SA38SA39SA40SA41SA42SA43SA44SA45SA46SA47SA48SA49SA50
Sector Address
A20–A12000000000000000001000000010000000011000000100000000101000000110000000111000001xxx000010xxx000011xxx000100xxx000101xxx000110xxx000111xxx001000xxx001001xxx001010xxx001011xxx001100xxx001101xxx001110xxx001111xxx010000xxx010001xxx010010xxx010011xxx010100xxx010101xxx010110xxx010111xxx011000xxx011001xxx011010xxx011011xxx011100xxx011101xxx011110xxx011111xxx100000xxx100001xxx100010xxx100011xxx100100xxx100101xxx100110xxx100111xxx101000xxx101001xxx101010xxx101011xxx
Bottom Boot Sector Addresses(Am29LV320DB)
Sector Size(Kbytes/Kwords)
8/48/48/48/48/48/48/48/4/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32
(x8)
Address Range000000h-001FFFh002000h-003FFFh004000h-005FFFh006000h-007FFFh008000h-009FFFh00A000h-00BFFFh00C000h-00DFFFh00E000h-00FFFFh010000h-01FFFFh020000h-02FFFFh030000h-03FFFFh040000h-04FFFFh050000h-05FFFFh060000h-06FFFFh070000h-07FFFFh080000h-08FFFFh090000h-09FFFFh0A0000h-0AFFFFh0B0000h-0BFFFFh0C0000h-0CFFFFh0D0000h-0DFFFFh0E0000h-0EFFFFh0F0000h-0FFFFFh100000h-10FFFFh110000h-11FFFFh120000h-12FFFFh130000h-13FFFFh140000h-14FFFFh150000h-15FFFFh160000h-16FFFFh170000h-17FFFFh180000h-18FFFFh190000h-19FFFFh1A0000h-1AFFFFh1B0000h-1BFFFFh1C0000h-1CFFFFh1D0000h-1DFFFFh1E0000h-1EFFFFh1F0000h-1FFFFFh200000h-20FFFFh210000h-21FFFFh220000h-22FFFFh230000h-23FFFFh240000h-24FFFFh250000h-25FFFFh260000h-26FFFFh270000h-27FFFFh280000h-28FFFFh290000h-29FFFFh2A0000h-2AFFFFh2B0000h-2BFFFFh
(x16)
Address Range000000h–000FFFh001000h–001FFFh002000h–002FFFh003000h–003FFFh004000h–004FFFh005000h–005FFFh006000h–006FFFh007000h–007FFFh008000h–00FFFFh010000h–017FFFh018000h–01FFFFh020000h–027FFFh028000h–02FFFFh030000h–037FFFh038000h–03FFFFh040000h–047FFFh048000h–04FFFFh050000h–057FFFh058000h–05FFFFh060000h–067FFFh068000h–06FFFFh070000h–077FFFh078000h–07FFFFh080000h–087FFFh088000h–08FFFFh090000h–097FFFh098000h–09FFFFh0A0000h–0A7FFFh0A8000h–0AFFFFh0B0000h–0B7FFFh0B8000h–0BFFFFh0C0000h–0C7FFFh0C8000h–0CFFFFh0D0000h–0D7FFFh0D8000h–0DFFFFh0E0000h–0E7FFFh0E8000h–0EFFFFh0F0000h–0F7FFFh0F8000h–0FFFFFh100000h–107FFFh108000h–10FFFFh110000h–117FFFh118000h–11FFFFh120000h–127FFFh128000h–12FFFFh130000h–137FFFh138000h–13FFFFh140000h–147FFFh148000h–14FFFFh150000h–157FFFh158000h–15FFFFh
14Am29LV320DSeptember 19, 2003
Table 4.
SectorSA51SA52SA53SA54SA55SA56SA57SA58SA59SA60SA61SA62SA63SASA65SA66SA67SA68SA69SA70
Bottom Boot Sector Addresses(Am29LV320DB) (Continued)
Sector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32
(x8)
Address Range2C0000h-2CFFFFh2D0000h-2DFFFFh2E0000h-2EFFFFh2F0000h-2FFFFFh300000h-30FFFFh310000h-31FFFFh320000h-32FFFFh330000h-33FFFFh340000h-34FFFFh350000h-35FFFFh360000h-36FFFFh370000h-37FFFFh380000h-38FFFFh390000h-39FFFFh3A0000h-3AFFFFh3B0000h-3BFFFFh3C0000h-3CFFFFh3D0000h-3DFFFFh3E0000h-3EFFFFh3F0000h-3FFFFFh
(x16)
Address Range160000h–167FFFh168000h–16FFFFh170000h–177FFFh178000h–17FFFFh180000h–187FFFh188000h–18FFFFh190000h–197FFFh198000h–19FFFFh1A0000h–1A7FFFh1A8000h–1AFFFFh1B0000h–1B7FFFh1B8000h–1BFFFFh1C0000h–1C7FFFh1C8000h–1CFFFFh1D0000h–1D7FFFh1D8000h–1DFFFFh1E0000h–1E7FFFh1E8000h–1EFFFFh1F0000h–1F7FFFh1F8000h–1FFFFFh
Sector Address
A20–A12101100xxx101101xxx101110xxx101111xxx111000xxx110001xxx110010xxx110011xxx110100xxx110101xxx110110xxx110111xxx111000xxx111001xxx111010xxx111011xxx111100xxx111101xxx111110xxx111111xxx
Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 5.
Sector Address
A20–A12000000xxx
Bottom Boot SecSiTM Sector Addresses
Sector Size(Kbytes/Kwords)
/32
(x8)
Address Range000000h-00FFFFh
(x16)
Address Range00000h-07FFFh
September 19, 2003Am29LV320D15
Autoselect Mode
The autoselect mode provides manufacturer and de-vice identification, and sector protection verification,through identifier codes output on DQ7–DQ0. Thismode is primarily intended for programming equip-ment to automatically match a device to be pro-grammed with its corresponding programmingalgorithm. However, the autoselect codes can also beaccessed in-system through the command register.When using programming equipment, the autoselectmode requires VID (11.5 V to 12.5 V) on address pinA9. Address pins A6, A1, and A0 must be as shown in
Table 6.
Table 6. In addition, when verifying sector protection,the sector address must appear on the appropriatehighest order address bits (see Tables 2–5). Table 6shows the remaining address bits that are don’t care.When all necessary bits have been set as required,the programming equipment may then read the corre-sponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the hostsystem can issue the autoselect command via thecommand register, as shown in Table 14. This methoddoes not require VID. Refer to the Autoselect Com-mand Sequence section for more information.
Autoselect Codes (HighVoltageMethod)
A20to A12XXSA
A11toA10XXX
A8toA7XXX
A5toA2XXX
DQ8 to DQ15
A1LLH
A0LHL
BYTE#BYTE# = VIH= VIL
X22hX
XXX
DQ7
toDQ001hF6 (T), F9h (B)01h (protected),00h (unprotected)99h (factory locked),19h (not factory
locked)
Description
Manufacturer ID: AMDDevice ID: Am29LV320DSector Protection Verification
SecSiTM Sector Indicator Bit (DQ7)
CE#LLL
OE#LLL
WE#HHH
A9VIDVIDVID
A6LLL
LLHXXVIDXLXHHXX
Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
16Am29LV320DSeptember 19, 2003
Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables bothprogram and erase operations in any sector. The hard-ware sector unprotection feature re-enables both pro-gram and erase operations in previously protectedsectors. Sector protection/unprotection can be imple-mented via two methods.
(Note: For the following discussion, the term “sector”applies to both sectors and sector blocks. A sectorblock consists of two or more adjacent sectors that areprotected or unprotected at the same time (see Tables7 and 8).Table 7.
Top Boot Sector/Sector Block Addresses forProtection/Unprotection
Sector/Sector Block
Size
Table 8.Bottom Boot Sector/Sector Block AddressesforProtection/Unprotection
Sector / Sector
Block
A20–A12111111XXX,111110XXX,111101XXX,111100XXX1110XXXXX1101XXXXX1100XXXXX1011XXXXX1010XXXXX1001XXXXX1000XXXXX0111XXXXX0110XXXXX0101XXXXX0100XXXXX0011XXXXX0010XXXXX0001XXXXX000011XXX,000010XXX,000001XXX000000111000000110000000101000000100000000011000000010000000001000000000
Sector/Sector Block
Size
SA70-SA67256 (4x) Kbytes
SA66-SA63SA62-SA59SA58-SA55SA54-SA51SA50-SA47SA46-SA43SA42-SA39SA38-SA35SA34-SA31SA30-SA27SA26-SA23SA22–SA19SA18-SA15SA14-SA11SA10-SA8SA7SA6SA5SA4SA3SA2SA1SA0
256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes192 (3x) Kbytes
8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes
Sector / Sector
Block A20–A12000000XXX,000001XXX,000010XXX000011XXX0001XXXXX0010XXXXX0011XXXXX0100XXXXX0101XXXXX0110XXXXX0111XXXXX1000XXXXX1001XXXXX1010XXXXX1011XXXXX1100XXXXX1101XXXXX1110XXXXX111100XXX,111101XXX,111110XXX111111000111111001111111010111111011111111100111111101111111110111111111
SA0-SA3256 (4x) Kbytes
SA4-SA7SA8-SA11SA12-SA15SA16-SA19SA20-SA23SA24-SA27SA28-SA31SA32-SA35SA36-SA39SA40-SA43SA44-SA47SA48-SA51SA52-SA55SA56-SA59SA60-SA62SA63SASA65SA66SA67SA68SA69SA70
256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes192 (3x) Kbytes
8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes
Sector Protection and unprotection requires VID on theRESET# pin only, and can be implemented eitherin-system or via programming equipment. Figure 2shows the algorithms and Figure 25 shows the timingdiagram. This method uses standard microprocessorbus cycle timing. For sector unprotect, all unprotectedsectors must first be protected prior to the first sectorunprotect write cycle.
The sector unprotect algorithm unprotects all sectorsin parallel. All previously protected sectors must be in-dividually re-protected. To change data in protectedsectors efficiently, the temporary sector unprotectfunction is available. See “Temporary Sector Unpro-tect”.
September 19, 2003Am29LV320D17
The alternate method intended only for programmingequipment, and requires VID on address pin A9 andOE#. This method is compatible with programmer rou-tines written for earlier 3.0 volt-only AMD flash de-vices. For detailed information, contact an AMDrepresentative.
The device is shipped with all sectors unprotected.AMD offers the option of programming and protectingsectors at its factory prior to shipping the devicethrough AMD’s ExpressFlash™ Service. Contact anAMD representative for details.
It is possible to determine whether a sector is pro-tected or unprotected. See the Autoselect Mode sec-tion for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-ously protected sectors to change data in-system. TheSector Unprotect mode is activated by setting the RE-SET# pin to VID (11.5 V – 12.5 V). During this mode,formerly protected sectors can be programmed orerased by selecting the sector addresses. Once VID isremoved from the RESET# pin, all the previously pro-tected sectors are protectedagain. Figure 1 shows thealgorithm, and Figure 23 shows the timing diagrams,for this feature.
Write Protect (WP#)
The Write Protect function provides a hardwaremethod of protecting certain boot sectors withoutusing VID. This function is one of two provided by theWP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the de-vice disables program and erase functions in the two“outermost” 8 Kbyte boot sectors independently ofwhether those sectors were protected or unprotectedusing the method described in “Sector/Sector BlockProtection and Unprotection”. The two outermost 8Kbyte boot sectors are the two sectors containing thelowest addresses in a bottom-boot-configured device,or the two sectors containing the highest addresses ina top-boot-configured device.
If the system asserts VIH on the WP#/ACC pin, the de-vice reverts to whether the two outermost 8K Byteboot sectors were last set to be protected or unpro-tected. That is, sector protection or unprotection forthese two sectors depends on whether they were lastprotected or unprotected using the method describedin “Sector/Sector Block Protection and Unprotection”.Note that the WP#/ACC pin must not be left floating orunconnected; inconsistent behavior of the device mayresult.
START
RESET# = VID
(Note 1)Perform Erase orProgram Operations
RESET# = VIH
Temporary SectorUnprotect Completed
(Note 2)
Notes:
1.All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).2.All previously protected sectors are protected once
again.
Figure 1.Temporary Sector Unprotect Operation
18Am29LV320DSeptember 19, 2003
STARTPLSCNT = 1RESET# = VIDWait 1 µsProtect all sectors:The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 µsTemporary SectorUnprotect ModeNoFirst Write Cycle = 60h?YesSet up sectoraddressSector Protect:Write 60h to sectoraddress withA6 = 0, A1 = 1, A0 = 0Wait 150 µsVerify Sector Protect: Write 40h to sector addresswith A6 = 0, A1 = 1, A0 = 0Read from sector addresswith A6 = 0, A1 = 1, A0 = 0NoNoFirst Write Cycle = 60h?YesAll sectorsprotected?YesSet up first sectoraddressSector Unprotect:Write 60h to sectoraddress withA6 = 1, A1 = 1, A0 = 0Temporary SectorUnprotect ModeIncrementPLSCNTResetPLSCNT = 1Wait 15 msVerify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0Read from sector addresswith A6 = 1, A1 = 1, A0 = 0Set upnext sectoraddressNoNoPLSCNT= 25?YesData = 01h?YesYesDevice failedProtect anothersector?NoRemove VID from RESET#Write reset commandIncrementPLSCNTNoNoPLSCNT= 1000?YesData = 00h?YesDevice failedLast sectorverified?YesNoSector ProtectAlgorithmSector ProtectcompleteSector UnprotectAlgorithmRemove VID from RESET#Write reset commandSector UnprotectcompleteFigure 2.In-System Sector Protect/UnprotectAlgorithms
September 19, 2003Am29LV320D19
SecSiTM Sector (Secured Silicon) Flash Memory Region
The Secured Silicon Sector (SecSi Sector) featureprovides a Flash memory region that enables perma-nent part identification through an Electronic SerialNumber (ESN). The SecSi Sector uses a SecSi SectorIndicator Bit (DQ7) to indicate whether or not theSecSi Sector is locked when shipped from the factory.This bit is permanently set at the factory and cannotbe changed, which prevents cloning of a factorylocked part. This ensures the security of the ESN oncethe product is shipped to the field. Note that theAm29LV320D has a SecSi Sector size of Kbytes. AMD devices designated as replacementsor substitutes, such as the Am29LV320M, will have256 bytes. This should be considered during sys-tem design.
AMD offers the device with the SecSi Sector eitherfactory locked or customer lockable. The fac-tory-locked version is always protected when shippedfrom the factory, and has the SecSi Sector IndicatorBit permanently set to a “1.” The customer-lockableversion is shipped with the SecSi Sector unprotected,allowing customers to utilize the that sector in anymanner they choose. The customer-lockable versionhas the SecSi Sector Indicator Bit permanently set to a“0.” Thus, the SecSi Sector Indicator Bit prevents cus-tomer-lockable devices from being used to replace de-vices that are factory locked.
The system accesses the SecSi Sector through acommand sequence (see “Enter SecSiTM Sector/ExitSecSi Sector CommandSequence”). After the systemhas written the Enter SecSi Sector command se-quence, it may read the SecSi Sector by using the ad-dresses normally occupied by the boot sectors. Thismode of operation continues until the system issuesthe Exit SecSi Sector command sequence, or untilpower is removed from the device. On power-up, orfollowing a hardware reset, the device reverts to send-ing commands to the boot sectors.
Factory Locked: SecSi Sector Programmed andProtectedattheFactory
In a factory locked device, the SecSi Sector is pro-tected when the device is shipped from the factory.The SecSi Sector cannot be modified in any way. Thedevice is available preprogrammed with one of the fol-lowing:
■A random, secure ESN only
■Customer code through the ExpressFlash service■Both a random, secure ESN and customer codethrough the ExpressFlash service.
In devices that have an ESN, a Bottom Boot devicewill have the 16-byte (8-word) ESN in sector 0 at ad-dresses 00000h–0000Fh in byte mode (or00000h–00007h in word mode). In the Top Boot de-vice the ESN will be in sector 63 at addresses3F0000h–3F000Fh in byte mode (or1F8000h–1F8007h in word mode). Note that in up-coming top boot versions of this device, the ESN willbe located in sector 70 at addresses3F000h–3F00Fh in byte mode (or1FF000h–1FF007h in word mode).
Customers may opt to have their code programmed byAMD through the AMD ExpressFlash service. AMDprograms the customer’s code, with or without the ran-dom ESN. The devices are then shipped from AMD’sfactory with the SecSi Sector permanently locked.Contact an AMD representative for details on usingAMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT Programmed orProtectedattheFactory
The customer lockable version allows the SecSi Sec-tor to be programmed once and then permanentlylocked after it has shipped from AMD. Note that theAm29LV320D has a SecSi Sector size of Kbytes. AMD devices designated as replacementsor substitutes, such as the Am29LV320M, will have256 bytes. This should be considered during sys-tem design. Additionally, note the change in thelocation of the ESN in upcoming top boot factorylocked devices. Note that the accelerated program-EE
ming (ACC) and unlock bypass functions are notavailable when programming the SecSi Sector.The SecSi Sector area can be protected using the fol-lowing procedures:
■Write the three-cycle Enter SecSi Region commandsequence, and then follow the in-system sector pro-tect algorithm as shown in Figure 2, except that RE-SET# may be at either VIH or VID. This allowsin-system protection of the SecSi Sector withoutraising any device pin to a high voltage. Note thatthis method is only applicable to the SecSi Sector.■To verify the protect/unprotect status of the SecSiSector, follow the algorithm shown in Figure 3.Once the SecSi Sector is locked and verified, the sys-tem must write the Exit SecSi Sector Region com-mand sequence to return to reading and writing theremainder of the array.
The SecSi Sector protection must be used with cau-tion since, once protected, there is no procedure avail-able for unprotecting the SecSi Sector area and noneof the bits in the SecSi Sector memory space can bemodified in any way.
20Am29LV320DSeptember 19, 2003
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#or WE# do not initiate a write cycle.
STARTRESET# =VIH or VIDWait 1 µsWrite 60h to any addressIf data = 00h, SecSi Sector isunprotected.If data = 01h, SecSi Sector isprotected.Logical Inhibit
Write cycles are inhibited by holding any one of OE# =VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,CE# and WE# must be a logical zero while OE# is alogical one.
Power-Up Write Inhibit
Remove VIH or VID from RESET#Write reset commandSecSi SectorProtect VerifycompleteWrite 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0Read from SecSi Sector addresswith A6 = 0, A1 = 1, A0 = 0If WE# = CE# = VIL and OE# = VIH during power up,the device does not accept commands on the risingedge of WE#. The internal state machine is automati-cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-lines device and host system software interrogationhandshake, which allows specific vendor-specifiedsoftware algorithms to be used for entire families ofdevices. Software support can then be device-inde-pendent, JEDEC ID-independent, and forward- andbackward-compatible for the specified flash devicefamilies. Flash vendors can standardize their existinginterfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-tem writes the CFI Query command, 98h, to address55h in word mode (or address AAh in byte mode), anytime the device is ready to read array data. The sys-tem can read CFI information at the addresses givenin Tables 9–12. To terminate reading CFI data, thesystem must write the reset command.
The system can also write the CFI query commandwhen the device is in the autoselect mode. The deviceenters the CFI query mode, and the system can readCFI data at the addresses given in Tables 9–12. Thesystem must write the reset command to return the de-vice to the reading array data.
For further information, please refer to the CFI Specifi-cation and CFI Publication 100, available via theWorld Wide Web at http://www.amd.com/flash/cfi. Al-ternatively, contact an AMD representative for copiesof these documents.
Figure 3.SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cyclesfor programming or erasing provides data protectionagainst inadvertent writes (refer to Table 14 for com-mand definitions). In addition, the following hardwaredata protection measures prevent accidental erasureor programming, which might otherwise be caused byspurious system level signals during VCC power-upand power-down transitions, or from system noise.Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-cept any write cycles. This protects data during VCCpower-up and power-down. The command registerand all internal program/erase circuits are disabled,and the device resets to the read mode. Subsequentwrites are ignored until VCC is greater than VLKO. Thesystem must provide the proper signals to the controlpins to prevent unintentional writes when VCC isgreater than VLKO.
September 19, 2003Am29LV320D21
Table 9.
Addresses(Word Mode)
10h11h12h13h14h15h16h17h18h19h1Ah
Addresses(Byte Mode)
20h22h24h26h28h2Ah2Ch2Eh30h32h34h
Data0051h0052h0059h0002h0000h0040h0000h0000h0000h0000h0000h
CFI Query Identification String
Description
Query Unique ASCII string “QRY”
Primary OEM Command SetAddress for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 10.
Addresses(Word Mode)
1Bh1Ch1Dh1Eh1Fh20h21h22h23h24h25h26h
Addresses(Byte Mode)
36h38h3Ah3Ch3Eh40h42h44h46h48h4Ah4Ch
Data0027h0036h0000h0000h0004h0000h000Ah0000h0005h0000h0004h0000h
System Interface String
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)VPP Max. voltage (00h = no VPP pin present)Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)Max. timeout for byte/word write 2N times typicalMax. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
22Am29LV320DSeptember 19, 2003
Table 11.
Addresses(Word Mode)
27h28h29h2Ah2Bh2Ch2Dh2Eh2Fh30h31h32h33h34h35h36h37h38h39h3Ah3Bh3Ch
Addresses(Byte Mode)
4Eh50h52h54h56h58h5Ah5Ch5Eh60h62hh66h68h6Ah6Ch6Eh70h72h74h76h78h
Data0016h0002h0000h0000h0000h0002h0007h0000h0020h0000h003Eh0000h0000h0001h0000h0000h0000h0000h0000h0000h0000h0000h
Device Geometry Definition
Description
Device Size = 2N byte
Flash Device Interface description (refer to CFI publication 100)Max. number of bytes in multi-byte write = 2N (00h = not supported)
Number of Erase Block Regions within deviceErase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
September 19, 2003Am29LV320D23
Table 12.
Addresses(Word Mode)
40h41h42h43h44h45h
Addresses(Byte Mode)
80h82h84h86h88h8Ah
Primary Vendor-Specific Extended Query
Description
Query-unique ASCII string “PRI”Major version number, ASCIIMinor version number, ASCIIAddress Sensitive Unlock (Bits 1-0)0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2)
Data0050h0052h0049h0031h0031h0000h
46h47h48h49h4Ah4Bh4Ch4Dh
8Ch8Eh90h92h94h96h98h9Ah
0002h0004h0001h0004h0000h0000h0000h00B5h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & WriteSector Protect
0 = Not Supported, X = Number of sectors in per groupSector Temporary Unprotect
00 = Not Supported, 01 = SupportedSector Protect/Unprotect scheme 04 = 29LV800 modeSimultaneous Operation00 = Not Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word PageACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mVACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mVTop/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
4Eh9Ch00C5h
4Fh9Eh000Xh
24Am29LV320DSeptember 19, 2003
COMMAND DEFINITIONS
Writing specific address and data commands or se-quences into the command register initiates device op-erations. Table 14 defines the valid register commandsequences. Note that writing incorrect address anddata values or writing them in the improper sequencemay place the device in an unknown state. A resetcommand is required to return the device to normaloperation.
All addresses are latched on the falling edge of WE#or CE#, whichever happens later. All data is latched onthe rising edge of WE# or CE#, whichever happensfirst. Refer to the AC Characteristics section for timingdiagrams.
program command sequence is written to a sector thatis in the Erase Suspend mode, writing the resetcommand returns the device to the erase-sus-pend-read mode. Once programming begins, how-ever, the device ignores reset commands until theoperation is complete.
The reset command may be written between the se-quence cycles in an autoselect command sequence.Once in the autoselect mode, the reset commandmust be written to return to the read mode. If the de-vice entered the autoselect mode while in the EraseSuspend mode, writing the reset command returns thedevice to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,writing the reset command returns the device to theread mode (or erase-suspend-read mode if the devicewas in Erase Suspend).
Reading Array Data
The device is automatically set to reading array dataafter device power-up. No commands are required toretrieve data. The device is ready to read array dataafter completing an Embedded Program or EmbeddedErase algorithm.
After the device accepts an Erase Suspend command,the device enters the erase-suspend-read mode, afterwhich the system can read data from anynon-erase-suspended sector. After completing a pro-gramming operation in the Erase Suspend mode, thesystem may once again read array data with the sameexception. See the Erase Suspend/Erase ResumeCommands section for more information.
The system must issue the reset command to returnthe device to the read (or erase-suspend-read) modeif DQ5 goes high during an active program or eraseoperation, or if the device is in the autoselect mode.See the next section, Reset Command, for more infor-mation.
See also Requirements for Reading Array Data in theDevice Bus Operations section for more information.The Read-Only Operations table provides the read pa-rameters, and Figure 14 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the hostsystem to read several identifier codes at specific ad-dresses:
Table 13.
Identifier CodeManufacturer IDDevice ID
SecSi Sector Factory ProtectSector Group Protect Verify
Autoselect Codes
Address00h01h03h(SA)02h
Table 14 shows the address and data requirements.This method is an alternative to that shown in Table 6,which is intended for PROM programmers and re-quires VID on address pin A9. The autoselect com-mand sequence may be written to an address withinsector that is either in the read or erase-suspend-readmode. The autoselect command may not be writtenwhile the device is actively programming or erasing.The autoselect command sequence is initiated by firstwriting two unlock cycles. This is followed by a thirdwrite cycle that contains the autoselect command. Thedevice then enters the autoselect mode. The systemmay read at any address any number of times withoutinitiating another autoselect command sequence.The system must write the reset command to return tothe read mode (or erase-suspend-read mode if the de-vice was previously in Erase Suspend).
Reset Command
Writing the reset command resets the device to theread or erase-suspend-read mode. Address bits aredon’t cares for this command.
The reset command may be written between the se-quence cycles in an erase command sequence beforeerasing begins. This resets the device to which thesystem was writing to the read mode. Once erasurebegins, however, the device ignores reset commandsuntil the operation is complete.
The reset command may be written between thesequence cycles in a program command sequencebefore programming begins. This resets the device towhich the system was writing to the read mode. If theSeptember 19, 2003
Enter SecSiTM Sector/Exit SecSi Sector CommandSequence
The SecSi Sector region provides a secured data areacontaining a random, sixteen-byte electronic serialnumber (ESN). The system can access the SecSi
Am29LV320D25
Sector region by issuing the three-cycle Enter SecSiSector command sequence. The device continues toaccess the SecSi Sector region until the system is-sues the four-cycle Exit SecSi Sector command se-quence. The Exit SecSi Sector command sequencereturns the device to normal operation. Table 14shows the address and data requirements for bothcommand sequences. Note that the ACC function andunlock bypass modes are not available when the de-vice has entered the SecSi Sector. See also “SecSiTMSector (Secured Silicon) Flash Memory Region” forfurther information.
cessful. However, a succeeding read will show that thedata is still “0.” Only erase operations can convert a“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-gram bytes or words to the device faster than usingthe standard program command sequence. The un-lock bypass command sequence is initiated by firstwriting two unlock cycles. This is followed by a thirdwrite cycle containing the unlock bypass command,20h. The device then enters the unlock bypass mode.A two-cycle unlock bypass program command se-quence is all that is required to program in this mode.The first cycle in this sequence contains the unlock by-pass program command, A0h; the second cycle con-tains the program address and data. Additional data isprogrammed in the same manner. This mode dis-penses with the initial two unlock cycles required in thestandard program command sequence, resulting infaster total programming time. Table 14 shows the re-quirements for the command sequence.
During the unlock bypass mode, only the Unlock By-pass Program and Unlock Bypass Reset commandsare valid. To exit the unlock bypass mode, the systemmust issue the two-cycle unlock bypass reset com-mand sequence. The first cycle must contain the data90h. The second cycle need only contain the data 00h.The device then returns to the read mode.
The device offers accelerated program operationsthrough the WP#/ACC pin. When the system assertsVHH on the WP#/ACC pin, the device automatically en-ters the Unlock Bypass mode. The system may thenwrite the two-cycle Unlock Bypass program commandsequence. The device uses the higher voltage on theWP#/ACC pin to accelerate the operation. Note thatthe WP#/ACC pin must not be at VHH any operationother than accelerated programming, or device dam-age may result. In addition, the WP#/ACC pin must notbe left floating or unconnected; inconsistent behaviorof the device may result.
Figure 4 illustrates the algorithm for the program oper-ation. Refer to the Erase and Program Operationstable in the AC Characteristics section for parameters,and Figure 18 for timing diagrams.
Byte/Word Program Command Sequence
The system may program the device by word or byte,depending on the state of the BYTE# pin. Program-ming is a four-bus-cycle operation. The program com-mand sequence is initiated by writing two unlock writecycles, followed by the program set-up command. Theprogram address and data are written next, which inturn initiate the Embedded Program algorithm. Thesystem is not required to provide further controls ortimings. The device automatically provides internallygenerated program pulses and verifies the pro-grammed cell margin. Table 14 shows the addressand data requirements for the byte program commandsequence. Note that the autoselect, SecSi Sector, andCFI modes are unavailable while a programming oper-ation is in progress.
When the Embedded Program algorithm is complete,the device then returns to the read mode and ad-dresses are no longer latched. The system can deter-mine the status of the program operation by usingDQ7, DQ6, or RY/BY#. Refer to the Write OperationStatus section for information on these status bits.Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that ahardware reset immediately terminates the programoperation. The program command sequence shouldbe reinitiated once the device has returned to the readmode, to ensure data integrity.
Programming is allowed in any sequence and acrosssector boundaries. A bit cannot be programmedfrom “0” back to a “1.” Attempting to do so maycause the device to set DQ5 = 1, or cause the DQ7and DQ6 status bits to indicate the operation was suc-
26Am29LV320DSeptember 19, 2003
RY/BY#. Refer to the Write Operation Status sectionfor information on these status bits.
STARTWrite ProgramCommand SequenceAny commands written during the chip erase operationare ignored. However, note that a hardware reset im-mediately terminates the erase operation. If that oc-curs, the chip erase command sequence should bereinitiated once the device has returned to readingarray data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-tion. Refer to the Erase and Program Operations ta-bles in the AC Characteristics section for parameters,and Figure 19 section for timing diagrams.
Embedded Programalgorithm in progressData Poll from SystemSector Erase Command Sequence
Verify Data?NoYesNoIncrement AddressLast Address?YesProgramming CompletedSector erase is a six bus cycle operation. The sectorerase command sequence is initiated by writing twounlock cycles, followed by a set-up command. Two ad-ditional unlock cycles are written, and are then fol-lowed by the address of the sector to be erased, andthe sector erase command. Table 14 shows the ad-dress and data requirements for the sector erase com-mand sequence. Note that the autoselect, SecSiSector, and CFI modes are unavailable while an eraseoperation is in progress.
The device does not require the system to preprogramprior to erase. The Embedded Erase algorithm auto-matically programs and verifies the entire memory foran all zero data pattern prior to electrical erase. Thesystem is not required to provide any controls or tim-ings during these operations.
After the command sequence is written, a sector erasetime-out of 50 µs occurs. During the time-out period,additional sector addresses and sector erase com-mands may be written. Loading the sector erase buffermay be done in any sequence, and the number of sec-tors may be from one sector to all sectors. The timebetween these additional cycles must be less than50µs, otherwise the last address and command maynot be accepted, and erasure may begin. It is recom-mended that processor interrupts be disabled duringthis time to ensure all commands are accepted. Theinterrupts can be re-enabled after the last SectorErase command is written. Any command other thanSector Erase or Erase Suspend during thetime-out period resets the device to the readmode. The system must rewrite the command se-quence and any additional addresses and commands.The system can monitor DQ3 to determine if the sec-tor erase timer has timed out (See the section on DQ3:Sector Erase Timer.). The time-out begins from the ris-ing edge of the final WE# pulse in the commandsequence.
When the Embedded Erase algorithm is complete, thedevice returns to reading array data and addressesare no longer latched. Note that while the Embedded
27
Note:See Table 14 for program command sequence.
Figure 4.Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erasecommand sequence is initiated by writing two unlockcycles, followed by a set-up command. Two additionalunlock write cycles are then followed by the chip erasecommand, which in turn invokes the Embedded Erasealgorithm. The device does not require the system topreprogram prior to erase. The Embedded Erase algo-rithm automatically preprograms and verifies the entirememory for an all zero data pattern prior to electricalerase. The system is not required to provide any con-trols or timings during these operations. Table 14shows the address and data requirements for the chiperase command sequence. Note that the autoselect,SecSi Sector, and CFI modes are unavailable while anerase operation is in progress.
When the Embedded Erase algorithm is complete, thedevice returns to the read mode and addresses are nolonger latched. The system can determine the statusof the erase operation by using DQ7, DQ6, DQ2, or
September 19, 2003Am29LV320D
Erase operation is in progress, the system can readdata from the non-erasing sector. The system can de-termine the status of the erase operation by readingDQ7, DQ6, DQ2, or RY/BY# in the erasing sector.Refer to the Write Operation Status section for infor-mation on these status bits.
Once the sector erase operation has begun, only theErase Suspend command is valid. All other com-mands are ignored. However, note that a hardwarereset immediately terminates the erase operation. Ifthat occurs, the sector erase command sequenceshould be reinitiated once the device has returned toreading array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-tion. Refer to the Erase and Program Operations ta-bles in the AC Characteristics section for parameters,and Figure 19 section for timing diagrams.
After an erase-suspended program operation is com-plete, the device returns to the erase-suspend-readmode. The system can determine the status of theprogram operation using the DQ7 or DQ6 status bits,just as in the standard Byte Program operation.Referto the Write Operation Status section for moreinformation.
In the erase-suspend-read mode, the system can alsoissue the autoselect command sequence. Refer to theAutoselect Mode and Autoselect Command Sequencesections for details.
To resume the sector erase operation, the systemmust write the Erase Resume command. Furtherwrites of the Resume command are ignored. AnotherErase Suspend command can be written after the chiphas resumed erasing.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the sys-tem to interrupt a sector erase operation and then readdata from, or program data to, any sector not selectedfor erasure. This command is valid only during thesector erase operation, including the 50 µs time-outperiod during the sector erase command sequence.The Erase Suspend command is ignored if written dur-ing the chip erase operation or Embedded Programalgorithm.
When the Erase Suspend command is written duringthe sector erase operation, the device requires a max-imum of 20 µs to suspend the erase operation. How-ever, when the Erase Suspend command is writtenduring the sector erase time-out, the device immedi-ately terminates the time-out period and suspends theerase operation.
After the erase operation has been suspended, thedevice enters the erase-suspend-read mode. The sys-tem can read data from or program data to any sectornot selected for erasure. (The device “erase sus-pends” all sectors selected for erasure.) Reading atany address within erase-suspended sectors pro-duces status information on DQ7–DQ0. The systemcan use DQ7, or DQ6 and DQ2 together, to determineif a sector is actively erasing or is erase-suspended.Refer to the Write Operation Status section for infor-mation on these status bits.
STARTWrite Erase Command Sequence(Notes 1, 2)Data Poll to Erasing Bank from SystemNoEmbedded Erasealgorithmin progressData = FFh?YesErasure CompletedNotes:
1.See Table 14 for erase command sequence.
2.See the section on DQ3 for information on the sector
erase timer.
Figure 5.Erase Operation
28Am29LV320DSeptember 19, 2003
Command Definitions
Table 14.
CommandSequence(Note 1)
Read (Note 6)Reset (Note 7)Autoselect (Note 8)Manufacturer IDDevice ID
SecSi Sector Factory Protect (Note 9)Sector Protect Verify (Note 10)
WordByteWordByteWordByteWordByteWordByteWordByteWordByteWordByte
CyclesFirstAddrRAXXX555AAA555AAA555AAA555AAA555AAA555AAA555AAA555AAAXXXXXX555AAA555AAABABA55AA
DataRDF0AAAAAAAAAAAAAAAAA090AAAAB03098
2AA5552AA5552AA5552AA5552AA5552AA5552AA5552AA555PAXXX2AA5552AA555
5555555555555555PD005555
555AAA555AAA
8080
555AAA555AAA
AAAA
2AA5552AA555
5555
555AAASA
1030
555AAA555AAA555AAA555AAA555AAA555AAA555AAA555AAA
9090909080A020
XXXPA
00PD
X00X01X02X03X06(SA)X02(SA)X04
01(see Table 6)99/1900/01
Am29LV320D Command Definitions
Bus Cycles (Notes 2–5)
Second Third Addr
Data
Addr
Data
Fourth Fifth Sixth Data
Addr
Data
Addr
Data
Addr
114444344
Enter SecSi™ Sector RegionExit SecSi Sector RegionProgramUnlock Bypass
32
2
6611
Unlock Bypass Program (Note 11)Unlock Bypass Reset (Note 12)Chip EraseSector Erase
Erase Suspend (Note 13)Erase Resume (Note 14)CFI Query (Note 15)
WordByteWordByteWordByte
1
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
Notes:
1.See Table 1 for description of bus operations.2.3.4.5.6.7.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
Unless otherwise noted, address bits A20–A11 are don’t cares.No unlock or command cycles required when device is in read mode.
The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information).
The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector.
9.The data is 99h for factory locked and 19h for not factory locked.
10.The data is 00h for an unprotected sector and 01h for a protected
sector. 11.The Unlock Bypass command is required prior to the Unlock
Bypass Program command.12.The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.13.The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.14.The Erase Resume command is valid only during the Erase
Suspend mode.
15.Command is valid when device is ready to read array data or when
device is in autoselect mode.
8.
September 19, 2003Am29LV320D29
WRITE OPERATION STATUS
The device provides several bits to determine the sta-tus of a program or erase operation: DQ2, DQ3, DQ5,DQ6, and DQ7. Table 15 and the following subsec-tions describe the function of these bits. DQ7 and DQ6each offer a method for determining whether a pro-gram or erase operation is complete or in progress.The device also provides a hardware-based outputsignal, RY/BY#, to determine whether an EmbeddedProgram or Erase operation is in progress or has beencompleted.
pleted the program or erase operation and DQ7 hasvalid data, the data outputs on DQ0–DQ6 may be stillinvalid. Valid data on DQ0–DQ7 will appear on suc-cessive read cycles.
Table 15 shows the outputs for Data# Polling on DQ7.Figure 6 shows the Data# Polling algorithm. Figure 20in the AC Characteristics section shows the Data#Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-tem whether an Embedded Program or Erase algo-rithm is in progress or completed, or whether a deviceis in Erase Suspend. Data# Polling is valid after therising edge of the final WE# pulse in the command se-quence.
During the Embedded Program algorithm, the deviceoutputs on DQ7 the complement of the datum pro-grammed to DQ7. This DQ7 status also applies to pro-gramming during Erase Suspend. When theEmbedded Program algorithm is complete, the deviceoutputs the datum programmed to DQ7. The systemmust provide the program address to read valid statusinformation on DQ7. If a program address falls within aprotected sector, Data# Polling on DQ7 is active forapproximately 1 µs, then the device returns to the readmode.
During the Embedded Erase algorithm, Data# Pollingproduces a “0” on DQ7. When the Embedded Erasealgorithm is complete, or if the device enters the EraseSuspend mode, Data# Polling produces a “1” on DQ7.The system must provide an address within any of thesectors selected for erasure to read valid status infor-mation on DQ7.
After an erase command sequence is written, if allsectors selected for erasing are protected, Data# Poll-ing on DQ7 is active for approximately 100 µs, thenthe device returns to the read mode. If not all selectedsectors are protected, the Embedded Erase algorithmerases the unprotected sectors, and ignores the se-lected sectors that are protected. However, if the sys-tem reads DQ7 at an address within a protectedsector, the status may not be valid.
Just prior to the completion of an Embedded Programor Erase operation, DQ7 may change asynchronouslywith DQ0–DQ6 while Output Enable (OE#) is assertedlow. That is, the device may change from providingstatus information to valid data on DQ7. Depending onwhen the system samples the DQ7 output, it may readthe status or valid data. Even if the device has com-STARTRead DQ7–DQ0Addr = VADQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSNotes:
1.VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6.Data# Polling Algorithm
30Am29LV320DSeptember 19, 2003
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pinwhich indicates whether an Embedded Algorithm is inprogress or complete. The RY/BY# status is valid afterthe rising edge of the final WE# pulse in the commandsequence. Since RY/BY# is an open-drain output, sev-eral RY/BY# pins can be tied together in parallel with apull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-ing or programming. (This includes programming inthe Erase Suspend mode.) If the output is high(Ready), the device is in the read mode, the standbymode, or in the erase-suspend-read mode. Table 15shows the outputs for RY/BY#.
Table 15 shows the outputs for Toggle Bit I on DQ6.Figure 7 shows the toggle bit algorithm. Figure 21 inthe “AC Characteristics” section shows the toggle bittiming diagrams. Figure 22 shows the differences be-tween DQ2 and DQ6 in graphical form. See also thesubsection on DQ2: Toggle Bit II.
STARTRead DQ7–DQ0DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an EmbeddedProgram or Erase algorithm is in progress or com-plete, or whether the device has entered the EraseSuspend mode. Toggle Bit I may be read at any ad-dress, and is valid after the rising edge of the finalWE# pulse in the command sequence (prior to theprogram or erase operation), and during the sectorerase time-out.
During an Embedded Program or Erase algorithm op-eration, successive read cycles to any address causeDQ6 to toggle. The system may use either OE# orCE# to control the read cycles. When the operation iscomplete, DQ6 stops toggling.
After an erase command sequence is written, if allsectors selected for erasing are protected, DQ6 tog-gles for approximately 100 µs, then returns to readingarray data. If not all selected sectors are protected, theEmbedded Erase algorithm erases the unprotectedsectors, and ignores the selected sectors that are pro-tected.
The system can use DQ6 and DQ2 together to deter-mine whether a sector is actively erasing or iserase-suspended. When the device is actively erasing(that is, the Embedded Erase algorithm is in progress),DQ6 toggles. When the device enters the Erase Sus-pend mode, DQ6 stops toggling. However, the systemmust also use DQ2 to determine which sectors areerasing or erase-suspended. Alternatively, the systemcan use DQ7 (see the subsection on DQ7: Data# Poll-ing).
If a program address falls within a protected sector,DQ6 toggles for approximately 1 µs after the programcommand sequence is written, then returns to readingarray data.
DQ6 also toggles during the erase-suspend-programmode, and stops toggling once the Embedded Pro-gram algorithm is complete.
NoRead DQ7–DQ0Toggle Bit = Toggle?YesNoDQ5 = 1?YesRead DQ7–DQ0TwiceToggle Bit = Toggle?YesProgram/EraseOperation Not Complete, Write Reset CommandNoProgram/EraseOperation CompleteNote:The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 7.Toggle Bit Algorithm
September 19, 2003Am29LV320D31
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing(that is, the Embedded Erase algorithm is in progress),or whether that sector is erase-suspended. Toggle BitII is valid after the rising edge of the final WE# pulse inthe command sequence.
DQ2 toggles when the system reads at addresseswithin those sectors that have been selected for era-sure. (The system may use either OE# or CE# to con-trol the read cycles.) But DQ2 cannot distinguishwhether the sector is actively erasing or is erase-sus-pended. DQ6, by comparison, indicates whether thedevice is actively erasing, or is in Erase Suspend, butcannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector andmode information. Refer to Table 15 to compare out-puts for DQ2 and DQ6.
Figure 7 shows the toggle bit algorithm in flowchartform, and the section “DQ2: Toggle Bit II” explains thealgorithm. See also the DQ6: Toggle Bit I subsection.Figure 21 shows the toggle bit timing diagram. Figure22 shows the differences between DQ2 and DQ6 ingraphical form.
at the beginning of the algorithm when it returns to de-termine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase timehas exceeded a specified internal pulse count limit.Under these conditions DQ5 produces a “1,” indicatingthat the program or erase cycle was not successfullycompleted.
The device may output a “1” on DQ5 if the system triesto program a “1” to a location that was previously pro-grammed to “0.” Only an erase operation canchange a “0” back to a “1.” Under this condition, thedevice halts the operation, and when the timing limithas been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must writethe reset command to return to the read mode (or tothe erase-suspend-read mode if the device was previ-ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, thesystem may read DQ3 to determine whether or noterasure has begun. (The sector erase timer does notapply to the chip erase command.) If additionalsectors are selected for erasure, the entire time-outalso applies after each additional sector erase com-mand. When the time-out period is complete, DQ3switches from a “0” to a “1.” If the time between addi-tional sector erase commands from the system can beassumed to be less than 50 µs, the system need notmonitor DQ3. See also the Sector Erase CommandSequence section.
After the sector erase command is written, the systemshould read the status of DQ7 (Data# Polling) or DQ6(Toggle Bit I) to ensure that the device has acceptedthe command sequence, and then read DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all fur-ther commands (except Erase Suspend) are ignoreduntil the erase operation is complete. If DQ3 is “0,” thedevice will accept additional sector erase commands.To ensure the command has been accepted, the sys-tem software should check the status of DQ3 prior toand following each subsequent sector erase com-mand. If DQ3 is high on the second status check, thelast command might not have been accepted.Table 15 shows the status of DQ3 relative to the otherstatus bits.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-ever the system initially begins reading toggle bit sta-tus, it must read DQ7–DQ0 at least twice in a row todetermine whether a toggle bit is toggling. Typically,the system would note and store the value of the tog-gle bit after the first read. After the second read, thesystem would compare the new value of the toggle bitwith the first. If the toggle bit is not toggling, the devicehas completed the program or erase operation. Thesystem can read array data on DQ7–DQ0 on the fol-lowing read cycle.
However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, the sys-tem also should note whether the value of DQ5 is high(see the section on DQ5). If it is, the system shouldthen determine again whether the toggle bit is tog-gling, since the toggle bit may have stopped togglingjust as DQ5 went high. If the toggle bit is no longertoggling, the device has successfully completed theprogram or erase operation. If it is still toggling, the de-vice did not completed the operation successfully, andthe system must write the reset command to return toreading array data.
The remaining scenario is that the system initially de-termines that the toggle bit is toggling and DQ5 hasnot gone high. The system may continue to monitorthe toggle bit and DQ5 through successive read cy-cles, determining the status as described in the previ-ous paragraph. Alternatively, it may choose to performother system tasks. In this case, the system must start32
Am29LV320DSeptember 19, 2003
Table 15.
Status
Standard Embedded Program AlgorithmModeEmbedded Erase Algorithm
Erase
Erase-Suspend-Suspended SectorErase
ReadSuspend Non-Erase
ModeSuspended Sector
Erase-Suspend-Program
Write Operation Status
DQ7(Note 2)DQ7#0
1DataDQ7#
DQ6ToggleToggleNo toggleDataToggle
DQ5(Note 1)
00
0Data0
DQ3N/A1N/ADataN/A
DQ2(Note 2)No toggleToggleToggleDataN/A
RY/BY#
00
110
Notes:
1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
September 19, 2003Am29LV320D33
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°CAmbient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°CVoltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 VA9, OE#, RESET#,
and WP#/ACC (Note 2). . . . . . . .–0.5 V to +12.5 VAll other pins (Note 1). . . . . . –0.5 V to VCC +0.5 VOutput Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1.Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins mayovershoot VSS to –2.0 V for periods of up to 20 ns.Maximum DC voltage on input or I/O pins is VCC +0.5 V.See Figure 8. During voltage transitions, input or I/O pinsmay overshoot to VCC +2.0 V for periods up to 20 ns. SeeFigure 9.2.Minimum DC input voltage on pins A9, OE#, RESET#,
and WP#/ACC is –0.5 V. During voltage transitions, A9,OE#, WP#/ACC, and RESET# may overshoot VSS to–2.0 V for periods of up to 20 ns. See Figure 8. MaximumDC input voltage on pin A9 is +12.5 V which mayovershoot to +14.0 V for periods up to 20 ns. MaximumDC input voltage on WP#/ACC is +9.5 V which mayovershoot to +12.0 V for periods up to 20 ns.3.No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greaterthan one second.Stresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device. Thisis a stress rating only; functional operation of the device atthese or any other conditions above those indicated in theoperational sections of this data sheet is not implied.Exposure of the device to absolute maximum ratingconditions for extended periods may affect device reliability.
+0.8 VVSS–0.5 VVSS–2.0 V
20 ns
20 ns
20 ns
Figure 8.Maximum Negative
OvershootWaveform
20 ns
VCC+2.0 VVCC+0.5 V
2.0 V
20 ns
20 ns
Figure 9.Maximum Positive
OvershootWaveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°CExtended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°CVCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which thefunctionality of the device is guaranteed.
34Am29LV320DSeptember 19, 2003
DC CHARACTERISTICSCMOS Compatible
Parameter Symbol
ILIILITILRILO
Parameter DescriptionInput Load CurrentA9 Input Load CurrentRESET# Input Load CurrentOutput Leakage Current
Test Conditions
VIN = VSS to VCC, VCC = VCC max
VCC = VCC max; A9 = 12.5 VVCC = VCC max; RESET# = 12.5 VVOUT = VSS to VCC, VCC = VCC max
CE# = VIL, OE# = VIH, Byte Mode
CE# = VIL, OE# = VIH, Word Mode
5 MHz1 MHz5 MHz1 MHz
102102150.20.20.2
–0.50.7 x VCC
VCC = 3.0 V ± 10%VCC = 3.0 V ± 10%
11.5Min
Typ
Max±3.03535±1.016 416 4305550.8VCC + 0.312.5
mAµAµAµAVVVmAUnitµAµAµAµA
ICC1
VCC Active Read Current (Notes 1, 2)
ICC2ICC3ICC4ICC5VILVIHVHHVIDVOLVOH1VOH2VLKO
VCC Active Write Current (Notes 2, 3)CE# = VIL, OE# = VIH, WE# = VILVCC Standby Current (Note 2)VCC Reset Current (Note 2)Automatic Sleep Mode (Notes 2, 4)Input Low VoltageInput High Voltage
Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration
Voltage for Autoselect and Temporary Sector UnprotectOutput Low VoltageOutput High Voltage
Low VCC Lock-Out Voltage (Note 5)
CE#, RESET# = VCC ± 0.3 VRESET# = VSS ± 0.3 VVIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V
11.512.5VVV
IOL = 4.0 mA, VCC = VCC min 0.45VCCIOH = –2.0 mA, VCC = VCC min 0.85 IOH = –100 µA, VCC = VCC min
VCC–0.42.3
2.5
V
Notes:
1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2.Maximum ICC specifications are tested with VCC = VCCmax.
3.ICC active while Embedded Erase or Embedded Program is in progress.
4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5.Not 100% tested.
September 19, 2003Am29LV320D35
DC CHARACTERISTICSZero-Power Flash
25Supply Current in mA20151050
0
500
1000
1500
2000Time in ns
Note:Addresses are switching at 1 MHz
2500300035004000
Figure 10.
ICC1 Current vs. Time (Showing Active and AutomaticSleepCurrents)
12
3.6 V
10
2.7 V
8Supply Current in mA6
4
2
01
Note:T = 25 °C
23
Frequency in MHz
Figure 11.
Typical ICC1 vs. Frequency
45
36Am29LV320DSeptember 19, 2003
TEST CONDITIONS
Table 16.
3.3 V
2.7 kΩ
Test Condition
Output Load
Output Load Capacitance, CL(including jig capacitance)
CL
6.2 kΩ
Input Rise and Fall TimesInput Pulse LevelsInput timing measurement reference levels
Note: Diodes are IN30 or equivalent
Output timing measurement reference levels
30
50.0–3.0
Test Specifications
90
1201 TTL gate
100
pFnsVUnit
DeviceUnderTest
1.5 V1.5
V
Figure 12. Test Setup
Key To Switching Waveforms
WAVEFORM
INPUTS
Steady
Changing from H to LChanging from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
3.0 V0.0 VInput1.5 VMeasurement Level1.5 VOutputFigure 13.Input Waveforms and Measurement Levels
September 19, 2003Am29LV320D37
AC CHARACTERISTICSRead-Only Operations
ParameterJEDECtAVAVtAVQVtELQVtGLQVtEHQZtGHQZtAXQX
Std.tRCtACCtCEtOEtDFtDFtOH
Description
Read Cycle Time (Note 1)Address to Output DelayChip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs FirstOutput Enable Hold Time (Note 1)
ReadToggle and Data# Polling
CE#, OE# = VIL
OE# = VILTest Setup
MinMaxMaxMaxMaxMaxMinMinMin
Speed Options9090909040
16160010
12012012012050
Unitnsnsnsnsnsnsnsnsns
tOEH
Notes:
1.Not 100% tested.
2.See Figure 12 and Table 16 for test specifications.
tRCAddressesCE#Addresses StabletACCtRHtRHOE#tOEHWE#HIGH ZtCEtOHOutput ValidHIGH ZtOEtDFOutputsRESET#RY/BY#0 VFigure 14.Read Operation Timings
38Am29LV320DSeptember 19, 2003
AC CHARACTERISTICSHardware Reset (RESET#)
ParameterJEDEC
StdtReadytReadytRPtRHtRPDtRB
Description
RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note)RESET# Pulse Width
Reset High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time
MaxMaxMinMinMinMin
All Speed Options
2050050050200
Unitµsnsnsnsµsns
Note: Not 100% tested.
RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#RESET#
tRPFigure 15.Reset Timings
September 19, 2003Am29LV320D39
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter JEDEC
Std.tELFL/tELFHtFLQZtFHQV
Description
CE# to BYTE# Switching Low or HighBYTE# Switching Low to Output HIGH ZBYTE# Switching High to Output Active
MaxMax Min
90 90
516
120120
Unitnsnsns
CE#
OE#
BYTE#
tELFL
BYTE#Switchingfrom wordto bytemode
DQ0–DQ14
Data Output(DQ0–DQ14)DQ15OutputtFLQZ
Data Output(DQ0–DQ7)AddressInput
DQ15/A-1
tELFH
BYTE#
BYTE#Switchingfrom byteto wordmode
DQ0–DQ14
Data Output(DQ0–DQ7)AddressInputtFHQV
Data Output(DQ0–DQ14)DQ15Output
DQ15/A-1
Figure 16.BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17.BYTE# Timings for Write Operations
40Am29LV320DSeptember 19, 2003
AC CHARACTERISTICS
Erase and Program Operations
ParameterJEDECtAVAVtAVWL
Std.tWCtAStASO
tWLAX
tAHtAHT
tDVWHtWHDX
tDStDHtOEPH
tGHWLtELWLtWHEHtWLWHtWHDL
tGHWLtCStCHtWPtWPHtSR/W
tWHWH1tWHWH1tWHWH2
tWHWH1tWHWH1tWHWH2tVCStRBtBUSY
Notes:
1.Not 100% tested.
2.See the “Erase And Programming Performance” section for more information.
Description
Write Cycle Time (Note 1)Address Setup Time
Address Setup Time to OE# low during toggle bit polling Address Hold Time
Address Hold Time From CE# or OE# high during toggle bit pollingData Setup TimeData Hold Time
Output Enable High during toggle bit pollingRead Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse WidthWrite Pulse Width High
Latency Between Read and Write OperationsProgramming Operation (Note 2)Accelerated Programming Operation, Word or Byte (Note 2)
Sector Erase Operation (Note 2)VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#Program/Erase Valid to RY/BY# Delay
ByteWord
MinMinMinMinMinMinMinMinMinMinMinMinMinMinTypTypTypTypMinMinMax
35
30091171.65009045
020000
50
45
0
50
9090
015
50120120
Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsµs
µssecµsnsns
September 19, 2003Am29LV320D41
AC CHARACTERISTICS
Program Command Sequence (last two cycles)tAStWCAddresses555hPAtAHCE#OE#tWPWE#tCStDSDatatDHPDtBUSYRY/BY#tVCSVCCStatusDOUTtRBtWPHtWHWH1Read Status Data (last two cycles)PAPAtCHA0hNotes:
1.PA = program address, PD = program data, DOUT is the true data at the program address.2.Illustration shows device in word mode.
Figure 18.Program Operation Timings
42Am29LV320DSeptember 19, 2003
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)tWCAddresses2AAhtASSA555h for chip eraseRead Status DataVAtAHVACE#tCHtWPWE#tCStDStDHData55h30h10 for Chip EraseInProgressCompleteOE#tWPHtWHWH2tBUSYRY/BY#tVCSVCCtRBNotes:1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).2.These waveforms are for the word mode.
Figure 19.Chip/Sector Erase Operation Timings
September 19, 2003Am29LV320D43
AC CHARACTERISTICS
tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplementTrueValid DataHigh ZVAVAtCEtOEtDFDQ0–DQ6tBUSYRY/BY#Status DataStatus DataTrueValid DataHigh ZNote:VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20.Data# Polling Timings (DuringEmbeddedAlgorithms)
44Am29LV320DSeptember 19, 2003
AC CHARACTERISTICS
tAHTAddressestAHTtASOCE#tOEHWE#tOEPHtCEPHtASOE#tDHDQ6/DQ2Valid DataValidStatustOEValidStatusValidStatusValid Data (first read)RY/BY#(second read)(stops toggling)Note:VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 21.Toggle Bit Timings (DuringEmbeddedAlgorithms)
EnterEmbeddedErasing
WE#
EraseSuspendEraseEnter EraseSuspend Program
EraseSuspendProgram
EraseResume
Erase Suspend
Read
Erase
EraseComplete
Erase SuspendRead
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 22.DQ2 vs. DQ6
September 19, 2003Am29LV320D45
AC CHARACTERISTICS
Temporary Sector Unprotect
ParameterJEDEC
Std.tVIDRtVHHtRSPtRRB
Description
VID Rise and Fall Time (See Note)VHH Rise and Fall Time (See Note)RESET# Setup Time for Temporary Sector Unprotect
RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect
MinMinMinMin
All Speed Options
50025044
Unitnsnsµsµs
Note: Not 100% tested.
VIDRESET#VSS, VIL,or VIHtVIDRProgram or Erase Command SequenceCE#tVIDRVIDVSS, VIL,or VIHWE#tRSPRY/BY#tRRB
Figure 23.Temporary Sector Unprotect TimingDiagram
VHHWP#/ACCVIL or VIHtVHHtVHHVIL or VIHFigure 24.Accelerated Program Timing Diagram
46Am29LV320DSeptember 19, 2003
AC CHARACTERISTICS
VIDVIHRESET#SA, A6,A1, A0Valid*Sector/Sector Block Protect or UnprotectValid*Verify40hSector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 msValid*Data60h60hStatus1 µsCE#WE#OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.Figure 25.Sector/Sector Block Protect and
UnprotectTimingDiagram
September 19, 2003Am29LV320D47
AC CHARACTERISTICS
Alternate CE# Controlled Erase and ProgramOperations
ParameterJEDECtAVAVtAVWLtELAXtDVEHtEHDXtGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH1tWHWH2
Std.tWCtAStAHtDStDHtGHELtWStWHtCPtCPHtWHWH1tWHWH1tWHWH2
Description
Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time
Read Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse WidthCE# Pulse Width HighProgramming Operation (Note 2)
Accelerated Programming Operation, Word or Byte (Note 2)
Sector Erase Operation (Note 2)
ByteWord
MinMinMinMinMinMinMinMinMinMinTypTypTypTyp
45
3091171.545
0000
50
9090
0
5050120120
Unitnsnsnsnsnsnsnsnsnsnsµs
µssec
Notes:
1.Not 100% tested.
2.See the “Erase And Programming Performance” section for more information.
48Am29LV320DSeptember 19, 2003
AC CHARACTERISTICS
555 for program2AA for erase PA for programSA for sector erase555 for chip erase Data# PollingPAAddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDStDHDatatRHA0 for program55 for erase PD for program30 for sector erase10 for chip erase tAStAHtWHWH1 or 2tBUSYDQ7#DOUTRESET#RY/BY#Notes:
1.Figure indicates last two bus cycles of a program or erase operation.
2.PA = program address, SA = sector address, PD = program data.
3.DQ7# is the complement of the data written to the device. DOUT is the data written to the device.4.Waveforms are for the word mode.
Figure 26.Alternate CE# Controlled Write (Erase/Program)OperationTimings
September 19, 2003Am29LV320D49
ERASE AND PROGRAMMING PERFORMANCE
ParameterSector Erase TimeChip Erase TimeByte Program Time
Accelerated Byte/Word Program TimeWord Program TimeChip Program Time (Note 3)
Byte ModeWord Mode
Typ (Note 1)
0.711297113624
300 21036010872Max (Note 2)
15
Unitsecsecµsµsµssec
Excludes system level overhead (Note 5)
Comments
Excludes 00h programming prior to erasure (Note 4)
Notes:
1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
14 for further information on command definitions.
6.The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pinsVCC Current
Min–1.0 V–1.0 V–100 mA
Max12.5 VVCC + 1.0 V+100 mA
Note:Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
CINCOUTCIN2
Notes:
1.Sampled, not 100% tested.
2.Test conditions TA = 25°C, f = 1.0 MHz.
Parameter DescriptionInput CapacitanceOutput CapacitanceControl Pin Capacitance
Test SetupVIN = 0VOUT = 0VIN = 0
TSOPFine-pitch BGA
TSOPFine-pitch BGA
TSOPFine-pitch BGA
Typ.28.55.47.53.9
Max7.55.0126.594.7
UnitpFpFpFpFpFpF
DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
Test Conditions
150°C125°C
Min1020
UnitYearsYears
50Am29LV320DSeptember 19, 2003
PHYSICAL DIMENSIONS
FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)6x12mm packageDwg rev AF; 1/2000xFBD 0486.00 mm x 12.00 mmPACKAGE1.200.200.940.8412.00 BSC6.00 BSC5.60 BSC4.00 BSC880.250.300.350.80 BSC0.40 BSCSeptember 19, 2003Am29LV320D51
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOPDwg rev AA; 10/9952Am29LV320DSeptember 19, 2003
REVISION SUMMARY
Revision A (November 1, 2000)
Initial release.
Erase and Program Operations table
Corrected to indicate tBUSY specification is a maximumvalue.
Revision A+1 (January 23, 2001)
Ordering Information
Corrected FBGA part number table to include bottomboot part numbers.
Revision B+1 (July 30, 2002)
Figure 3, SecSi Sector Protect Verify
Deleted fifth block in flowchart and modified text infourth block.
Revision A+2 (February 1, 2001)
Connection DiagramsCorrected FBGA ball matrix.
Revision C (October 25, 2002)
Distinctive Characteristics
Changed endurance from “write” to “erase” cycles.Connection Diagrams
Deleted ultrasonic reference and added packagetypes to special package handling text.Ordering Information
Added commercial temperature range and removedextended temperature range.SecSi Sector Flash Memory Region
Customer Lockable subsection: Deleted reference toalternate method of sector protection.Command DefinitionsNoted the following:
Autoselect, SecSi Sector, and CFI functions are notavailable during a program or erase operation. ACC and unlock bypass modes are not availablewhen the SecSi Sector is enabled.
Writing incorrect data or commands may place the de-vice in an unknown state. A reset command is then re-quired.
AC Characteristics
Read-only Operations; Word/Byte Configuration:Changed tDF and tFLQZ to 16 ns for all speed options.DC Characteristics
Deleted IACC and added ILR specifications from table. TSOP, SO, and BGA Package CapacitanceAdded BGA capacitance to table.
Revision A+3 (July 2, 2001)
Global
Changed data sheet status from Advance Informationto Preliminary.
Table 3, Top Boot SecSiTM Sector AddressesCorrected sector block size for SA60–SA62 to 3x.Sector/Sector Block Protection and UnprotectionNoted that sectors are erased in parallel.
SecSiTM Sector (Secured Silicon) Flash Memory Region
Noted changes for upcoming versions of these de-vices: reduced SecSi Sector size, different ESN loca-tion for top boot devices, and deletion of SecSi Sectorerase functionality. Current versions of these devicesremain unaffected.
Revision B (July 12, 2002)
Global
Deleted Preliminary status from document.Ordering InformationDeleted burn-in option.
Table 1, Am29LV320D Device Bus OperationsIn the legend, corrected VHH maximum voltage to 12.5V.
SecSiTM Sector (Secured Silicon) Flash Memory Region
Added description of SecSi Sector protection verifica-tion.
Autoselect Command SequenceClarified description of function.
Table 14, Am29LV320D Command DefinitionsCorrected autoselect codes for SecSi Sector FactoryProtect.
Revision C+1 (February 16, 2003)
Distinctive Characteristics
Added reference to MirrorBit in Secured Silicon section.
Added Sector Architecture section.
September 19, 2003Am29LV320D53
SecSi Sector Flash Memory Region
Referenced MirrorBit for an example in last sentenceof first paragraph.Command Definitions
Changed the first address of the Unlock Bypass Resetfrom BA to XXX.
Erase and Programming PerformanceCorrected the Sector Erase Time Typical to 0.7.
Revision C+2 (April 4, 2003)
Distinctive Characteristics
Clarified reference to MirrorBit in Secured Silicon sec-tion.
SecSi Sector Flash Memory Region
Clarified reference of MirrorBit for an example in lastsentence of first paragraph.
Revision C+3 (September 19, 2003)
Valid Combinations
Added the 90R package to table.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
54Am29LV320DSeptember 19, 2003
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